ASIC Design Engineer -Juniper Networks- 4 to 7 years
Kindly forward your resume to areef_6@yahoo.com only if your prior experience matches the below requirement.
"Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills".
ASIC Design Engineer
Experience : 4 – 7 yrs
Job Summary
Responsible for block level/ full chip ASIC design
Responsibilities
Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper's next generation of networking products.
Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
Develop module register specifications.
Need to make and maintain block schedule and complete tasks on or before time.
Work with verification engineers to close code coverage and ensure first-time working silicon.
Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
Mentor fresh graduate engineers with the design flow, strategy.
Qualification
Requires a BS/MS EE or equivalent and a minimum of 6+ years of ASIC design experience.
Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills.
Must have good leadership/communication skills.
Networking experience is highly desirable, but not required.
Track record of successfully design of ASIC's from start to finish.
Areef.
9740921221.
"Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills".
ASIC Design Engineer
Experience : 4 – 7 yrs
Job Summary
Responsible for block level/ full chip ASIC design
Responsibilities
Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper's next generation of networking products.
Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
Develop module register specifications.
Need to make and maintain block schedule and complete tasks on or before time.
Work with verification engineers to close code coverage and ensure first-time working silicon.
Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
Mentor fresh graduate engineers with the design flow, strategy.
Qualification
Requires a BS/MS EE or equivalent and a minimum of 6+ years of ASIC design experience.
Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills.
Must have good leadership/communication skills.
Networking experience is highly desirable, but not required.
Track record of successfully design of ASIC's from start to finish.
Areef.
9740921221.
0 Response to "ASIC Design Engineer -Juniper Networks- 4 to 7 years"
Post a Comment